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INTEGRATED CIRCUITS
DATA SHEET
TDA8766 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
Product specification Supersedes data of 2001 Apr 19 2002 Jul 02
Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
FEATURES * 10-bit resolution * 3.0 to 5.25 V operation * Sampling rate up to 20 MHz * DC sampling allowed * High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz; full-scale input at fclk = 20 MHz) * In-Range (IR) CMOS output * CMOS/TTL compatible digital inputs and outputs * External reference voltage regulator * Power dissipation only 53 mW (typical value) * Low analog input capacitance, no buffer amplifier required * Standby mode * No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL VDDA VDDD1 VDDD2 VDDO IDDA IDDD IDDO INL DNL fclk(max) Ptot PARAMETER analog supply voltage digital supply voltage 1 digital supply voltage 2 output stages supply voltage analog supply current digital supply current output stages supply current integral non-linearity differential non-linearity maximum clock frequency total power dissipation VDDA = VDDD = VDDO = 3.3 V fclk = 20 MHz; CL = 20 pF; ramp input fclk = 20 MHz; ramp input fclk = 20 MHz; ramp input CONDITIONS MIN. 3.0 3.0 3.0 3.0 - - - - - 20 - TYP. 3.3 3.3 3.3 3.3 7.5 7.5 1 1 0.25 - 53 APPLICATIONS
TDA8766
High-speed analog-to-digital conversion for: * Video data digitizing * Camera * Camcorder * Radio communication. GENERAL DESCRIPTION The TDA8766 is a 10-bit high-speed Analog-to-Digital Converter (ADC) for professional video and other applications. It converts with 3.0 to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows reduction of the device power consumption down to 4 mW.
MAX. 5.25 5.25 5.25 5.25 10 10 2 2 0.7 - 73
UNIT V V V V mA mA mA LSB LSB MHz mW
ORDERING INFORMATION TYPE NUMBER TDA8766G PACKAGE NAME LQFP32 DESCRIPTION plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm VERSION SOT401-1
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
BLOCK DIAGRAM
TDA8766
handbook, full pagewidth
V DDA 7
CLK 5
VDDD2 18
OE 16
CLOCK DRIVER V RT 15
6
STDBY
TDA8766
1 D9 31 D8 30 D7 RLAD 29 D6 28 D5 CMOS OUTPUTS MSB
analog voltage input
VI
14
ANALOG -TO - DIGITAL CONVERTER
LATCHES
27 D4 26 D3 25 D2 23 D1 22 D0
data outputs
V RM 11
LSB VDDO
VRB 10
20
IN-RANGE LATCH
CMOS OUTPUT
2
IR output
4 9 VSSA analog ground 19 VSSD2 digital ground 2 21 VSSO output ground 3 VSSD1
VDDD1
MLC853
digital ground 1
Fig.1 Block diagram.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
PINNING SYMBOL PIN D9 IR VSSD1 VDDD1 CLK STDBY VDDA n.c. VSSA VRB VRM n.c. n.c. VI VRT OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION data output; bit 9 (MSB) in-range data output digital ground 1 digital supply voltage 1 (3.0 to 5.25 V) clock input standby mode input analog supply voltage (3.0 to 5.25 V) not connected analog ground reference voltage BOTTOM input reference voltage MIDDLE input not connected not connected analog voltage input reference voltage TOP input output enable input (active LOW) VSSO D0 D1 n.c. D2 D3 D4 D5 D6 D7 D8 n.c. 21 22 23 24 25 26 27 28 29 30 31 32 SYMBOL PIN n.c. VDDD2 VSSD2 VDDO 17 18 19 20
TDA8766
DESCRIPTION not connected digital supply voltage 2 (3.0 to 5.25 V) digital ground 2 positive supply voltage for output stage (3.0 to 5.25 V) output stage ground data output; bit 0 (LSB) data output; bit 1 not connected data output; bit 2 data output; bit 3 data output; bit 4 data output; bit 5 data output; bit 6 data output; bit 7 data output; bit 8 not connected
32 n.c.
31 D8
30 D7
29 D6
28 D5
27 D4
26 D3
handbook, full pagewidth
25 D2
D9 IR VSSD1 VDDD1 CLK STDBY VDDA n.c.
1 2 3 4
24 n.c. 23 D1 22 D0 21 VSSO
TDA8766
5 6 7 8 20 VDDO 19 VSSD2 18 VDDD2 17 n.c.
VRB 10
VRM 11
n.c. 12
n.c. 13
VI 14
VRT 15
OE 16
9
MLC854
VSSA
Fig.2 Pin configuration.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDA VDDD VDDO VDD PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage difference VDDA - VDDD VDDD - VDDO VDDA - VDDO VI Vi(p-p) IO Tstg Tamb Tj Note input voltage AC input voltage for switching (peak-to-peak value) output current storage temperature ambient temperature junction temperature referenced to VSSA referenced to VSSD -1.0 -1.0 -1.0 -0.3 - - -55 -20 - +4.0 +4.0 +4.0 +7.0 CONDITIONS note 1 note 1 note 1 MIN. -0.3 -0.3 -0.3
TDA8766
MAX. +7.0 +7.0 +7.0 V V V V V V V V
UNIT
VDDD 10 +150 +75 150
mA C C C
1. The supply voltages VDDA, VDDD and VDDO may have any value between -0.3 and +7.0 V provided that the supply voltage differences VDD are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(jj-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 90 UNIT K/W
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
TDA8766
CHARACTERISTICS VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO short-circuited together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 to 70 C; typical values measured at Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDA VDDD1 VDDD2 VDDO VDD analog supply voltage digital supply voltage 1 digital supply voltage 2 output stages supply voltage voltage difference VDDA - VDDD VDDA - VDDO VDDD - VDDO IDDA IDDD IDDO Ptot Inputs CLOCK INPUT CLK (REFERENCED TO VSSD); note 1 VIL VIH IIL IIH Zi Ci VIL VIH IIL IIH IIL IIH Zi Ci LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance VDDD 3.6 V VDDD = 3.3 V VCLK = 0.3VDDD VCLK = 0.7VDDD fclk = 20 MHz fclk = 20 MHz 0 0.6VDDD 0.7VDDD -1 - - - 0 VDDD 3.6 V VDDD = 3.3 V LOW-level input current HIGH-level input current VIL = 0.3 VDDD VIH = 0.7 VDDD VI = VRB VI = VRT fi = 1 MHz fi = 1 MHz 0.6VDDD 0.7VDDD -1 - - - - - - - - 0 - 4 3 - - - - - 0 35 5 8 0.3VDDD V VDDD VDDD +1 5 - - V V A A k pF analog supply current digital supply current output stages supply current total power dissipation fclk = 20 MHz; ramp input; CL = 20 pF operating; VDD = 3.3 V standby mode -0.2 -0.2 -0.2 - - - - - - - - 7.5 7.5 1 53 4 +0.2 +0.2 +0.2 10 10 2 73 - V V V mA mA mA mW mW 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 5.25 5.25 5.25 5.25 V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
INPUTS OE AND STDBY (REFERENCED TO VSSD); see Tables 1 and 2 LOW-level input voltage HIGH-level input voltage 0.3VDDD V VDDD VDDD - 1 - - - - V V A A A A k pF
ANALOG INPUT VI (REFERENCED TO VSSA) LOW-level input current HIGH-level input current input impedance input capacitance
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. -
TDA8766
MAX.
UNIT
Reference voltages for resistor ladder; see Table 3 VRB VRT Vdiff(ref) Iref RLAD TCRLAD Voffset(B) Voffset(T) VI(p-p) Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO VSSD) VOL VOH IOZ LOW-level output voltage HIGH-level output voltage output current in 3-state mode IO = 1 mA IO = -1 mA 0.5 V < VO < VDDO 0 VDDO - 0.5 -20 - - - 0.5 VDDO +20 V V A reference voltage BOTTOM reference voltage TOP differential reference voltage VRT - VRB reference current ladder resistance temperature coefficient of ladder resistance offset voltage BOTTOM offset voltage TOP analog input voltage (peak-to-peak value) note 2 note 2 note 3 1.1 3.0 1.9 - - - - - - 1.66 1.2 3.3 2.1 7.2 290 539 1860 135 135 1.83 V V V mA m/K ppm mV mV V VDDA 3.0 - - - - - - 2.35
Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fclk(max) tCPH tCPL maximum clock frequency clock pulse width HIGH clock pulse width LOW 20 15 15 - - - - - - MHz ns ns
Analog signal processing (fclk = 20 MHz) LINEARITY INL DNL integral non-linearity differential non-linearity ramp input; see Fig.6 ramp input; see Fig.7 - - - - 1 0.25 4 4 2 0.7 6 6 LSB LSB
INPUT SET RESPONSE; see Fig.8; note 4 tSTLH tSTHL analog input settling time LOW-to-HIGH analog input settling time HIGH-to-LOW full-scale square wave full-scale square wave ns ns
HARMONICS; see Fig.9; note 5 THD total harmonic distortion fi = 1 MHz without harmonics; fi = 1 MHz - - -63 60 - - dB
SIGNAL-TO-NOISE RATIO; see Fig.9; note 5 S/N signal-to-noise ratio (full-scale) dB
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
SYMBOL PARAMETER CONDITIONS - - - - 5 VDDO = 4.75 V VDDO = 3.15 V 3-state output delay times; see Fig.5 tdZH tdZL tdHZ tdLZ td(stb)LH td(stb)HL Notes enable HIGH enable LOW disable HIGH disable LOW - - - - - - 14 16 16 14 - - 18 20 20 18 8 8 MIN. TYP. - - -
TDA8766
MAX.
UNIT
EFFECTIVE BITS; see Fig.9; note 5 EB effective bits fi = 300 kHz fi = 1 MHz fi = 3.58 MHz Timing (fclk = 20 MHz; CL = 20 pF); see Fig.4; note 6 tds th td sampling delay time output hold time output delay time - - 12 17 5 - 15 20 ns ns ns ns 9.5 9.3 8.0 bits bits bits
ns ns ns ns
Standby mode output delay times standby LOW-to-HIGH transition start-up HIGH-to-LOW transition 200 500 ns ns
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Analog input voltages producing code 0 up to and including 1023: a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 C. b) Voffset(T) (offset voltage TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to 1023 at Tamb = 25 C. 3. In order to ensure the optimum linearity performance of such converter architecture, the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. V RT - V RB a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter, R OB + R L + R OT RL to cover code 0 to code 1023, is V I = R L x I L = ----------------------------------------- x ( V RT - V RB ) = 0.871 x ( V RT - V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ---------------------------------------- will be kept reasonably constant from device to device. Consequently variation of the output R OB + R L + R OT codes at a given input voltage depends mainly on the difference VRT - VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input change (square-wave signal) in order to sample the signal and obtain correct output data.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
TDA8766
5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8k acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 6. Output data acquisition: the output data is available after the maximum delay time of td.
handbook, halfpage
VRT ROT RL VRM RLAD IL code 0 ROB VRB
MGD281
code 1023
Fig.3 Converter reference resistor ladder.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
Table 1 Mode selection OE 1 0 Table 2 Standby selection STDBY 1 0 Table 3 last logic state active D9 to D0 active (binary) D9 to D0 high impedance high impedance active IR
TDA8766
IDDA + IDDD 1.2 mA (typical value) 15 mA (typical value)
Output coding and input voltage (typical values; referenced to VSSA) BINARY OUTPUT BITS VI(p-p) <1.335 V 1.335 V : : : 3.165 V >3.165 V IR D9 0 1 1 : 1 1 0 0 0 0 : 1 1 1 D8 0 0 0 : 1 1 1 D7 0 0 0 : 1 1 1 D6 0 0 0 : 1 1 1 D5 0 0 0 : 1 1 1 D4 0 0 0 : 1 1 1 D3 0 0 0 : 1 1 1 D2 0 0 0 : 1 1 1 D1 0 0 0 : 1 1 1 D0 0 0 1 : 0 1 1
STEP Underflow 0 1 : 1022 1023 Overflow
handbook, full pagewidth
t CPL t CPH CLK 50%
sample N
sample N + 1
sample N + 2
Vl
t ds DATA D0 to D9 DATA N-2 DATA N-1 td
th VDDO DATA N DATA N+1
MGD346
50% 0V
Fig.4 Timing diagram.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
TDA8766
handbook, full pagewidth
V DDD OE 50 %
t dHZ HIGH 90 % output data t dLZ HIGH output data LOW 10 % 50 % t dZL LOW
t dZH
50 %
TEST V DDD 3.3 k TDA8766 20 pF OE fOE = 100 kHz. S1 t dLZ t dZL t dHZ t dZH
S1 VDDD VDDD GND GND
MLC855
Fig.5 Timing diagram and test conditions of 3-state output delay time.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
TDA8766
handbook, full pagewidth
0.6
MLD115
A (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
0
200
400
600
800 f (codes)
1000
1023
1100
Fig.6 Typical Integral Non-Linearity (INL) performance.
handbook, full pagewidth
0.25
MLD116
A (LSB) 0.15
0.05
-0.05
-0.15
-0.25
0
200
400
600
800 f (codes)
1000
1023
1100
Fig.7 Typical Differential Non-Linearity (DNL) performance.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
TDA8766
t STLH
handbook, full pagewidth
t STHL
code 1023 VI code 0 5 ns 5 ns 50 % 50 %
CLK
50 %
50 %
MBD875
2 ns
2 ns
Fig.8 Analog input settling-time diagram.
MLD117
handbook, full pagewidth
0
A (dB) 20
40
60
80
100
120 0 1.25 2.5 3.76 5.01 6.26 7.51 8.76 f (MHz) Effective bits: 9.59; THD = -76.60 dB. Harmonic levels (dB): 2nd = -81.85; 3rd = -87.56; 4th = -88.81; 5th = -88.96; 6th = -79.58. 10
Fig.9 Typical fast Fourier transform (fclk = 20 MHz; fi = 1 MHz).
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
INTERNAL PIN CONFIGURATION
TDA8766
handbook, halfpage
VDDO
handbook, halfpage
V DDA
D9 to D0, IR
VI
VSSO
MLC856
VSSA
MLC857
Fig.10 D9 to D0 and IR outputs.
Fig.11 VI analog input.
handbook, halfpage
VDDO
handbook, halfpage
VDDA
VRT OE, STDBY VRM VRB R LAD
VSSO
MLC858
VSSA
MLC859
Fig.12 OE and STDBY inputs.
Fig.13 VRB, VRM and VRT inputs.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
TDA8766
DDD handbook, halfpage
V
CLK
1/2V
DDD
VSSD
MLC860
Fig.14 CLK input.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number "AN00014").
TDA8766
handbook, full pagewidth
n.c. 32 D9 IR V SSD1 VDDD1 CLK STDBY VDDA n.c.
(2)
(2)
D8 31
D7 30
D6 29
D5 28
D4 27
D3 26
D2 25 24 23 22 21 n.c. D1 D0 VSSO VDDO VSSD2 VDDD2 n.c.
(2) (2)
1 2 3 4
TDA8766
5 6 7 8 9 VSSA 100 nF VSSA 100 nF VSSA 10 11 12 13 n.c.
(2)
20 19 18 17 14 VI (4) 15 VRT 16
(1) OE
(2) VRB(1) VRM (1) n.c. (3)
MLC861
100 nF VSSA
The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) (2) (3) (4) VRB, VRM and VRT are decoupled to VSSA. Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence. When VRM is not used, pin 11 can be left open-circuit, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14).
Fig.15 Application diagram.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm
TDA8766
SOT401-1
c y X
24 25
17 16 ZE
A
e E HE wM bp 32 1 8 9 L detail X Lp A A2 A1 pin 1 index (A 3)
e bp D HD
ZD wM B
vM A
vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.15 0.05 A2 1.5 1.3 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 5.1 4.9 E (1) 5.1 4.9 e 0.5 HD 7.15 6.85 HE 7.15 6.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT401-1 REFERENCES IEC 136E01 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
TDA8766
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
TDA8766
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Jul 02
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Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
TDA8766
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Jul 02
20
Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
NOTES
TDA8766
2002 Jul 02
21
Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
NOTES
TDA8766
2002 Jul 02
22
Philips Semiconductors
Product specification
10-bit high-speed 3.0 to 5.25 V analog-to-digital converter
NOTES
TDA8766
2002 Jul 02
23
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/05/pp24
Date of release: 2002
Jul 02
Document order number:
9397 750 10029

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